1. Field of the Invention
The present invention relates to a computer system, and more particularly to system and method for trapping bus cycles of the computer system.
2. Description of the Prior Art
Complete pre-silicon test of an integrated circuit is essential to the production quality of a computer system. Electronic systems are designed to operate in specific ways so as to perform specific functions. During the design process, designers have to debug the functionality of the computer system many times for minimizing or preventing from failures that may occur in manufacture or system operation. In general, the designer needs to gather enough bus cycles of the computer system for debugging purpose. Various hardware tools, such as Logic Analyzer (LA), Hardware ICE (in-circuit emulator), have been employed in verifying bus cycles of the computer system. However, such conventional system has a relative high cost due to extra hardware tools, and is not able to trap some specific bus cycles.
Please refer to FIG. 1, which is a block diagram of a conventional bus cycle trapping system. The system includes a central processing unit (CPU) 10, a north bridge 20 connected to the CPU 10, a south bridge 30 connected with peripheral devices (not shown) through a PCI (Peripheral Component Interconnect) bus 35, an AGP (Accelerated Graphics Port) device 40 and a memory 50 connected with the north bridge 20. The system further includes an LA (Logic Analyzer) 39 connected to the PCI bus 35 for trapping bus cycles. However, since AGP-to-Memory cycles are directly transferred from the AGP device 40 to the memory 50, as indicated by the numeral reference 45, without transmission through the PCI bus 35, the LA 39 is unable to detect any AGP-to-Memory cycles.
Now refer to FIG. 2, which is a block diagram of another conventional bus cycle trapping system. As shown in FIG. 2, the CPU 10 connects to the north bridge 20 through a host bus 15, a Hardware ICE (in-circuit emulator) 17 is connected to the host bus 15 for trapping a specific CPU-to-PCI configuration cycle. The CPU-to-PCI configuration cycle is composed of two writing cycles, which provide configuration address and configuration data 19 to the south bridge 30 respectively. The CPU 10 will send a large number of write cycles with configuration addresses to the south bridge 30. One disadvantage of such a system is that when the hardware ICE 17 is utilized to verify a specified CPU-to-PCI configuration cycle, the hardware ICE 17 has to check all of the write cycles with configuration address, which is time consuming and has low efficiency.